schema_editor/examples/simplified FRISC model/comdel.system

// Version 0.0.1
#include "libraries\frisc\vjezba1\FRISC.cdl"
#include "libraries\frisc\vjezba1\memory.cdl"



component System
{
  clock 100MHz;
	//glavnaSabirnica
	wire<32> ADR;
	wire<32> DATA;
	wire READ;
	wire WRITE;
	wired_and WAIT;
	wired_and INT0;
	wired_and INT1;
	wired_and INT2;
	wired_and INT3;
	wire<3> SIZE;
	wire --IACK;
	wire --BREQ;
	wire --BACK;


	//directRam
	wire INT;


	// components --------------------------------------------
	subcomponent Memorija memorija<false, 1, 65536, 8, 0>(ADR, DATA, READ, WRITE, SIZE, WAIT, *, *, *, INT);
	subcomponent FRISC procesor(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, INT1, INT2, INT3, --IACK, 1, *, INT, *, *, *);

	display {
		component { x: -377; y: -302; ref: "procesor"; }
		component { x: -56; y: -80; ref: "memorija"; }

		// glavnaSabirnica bus

		rectangle {
			x: -377; y: -106;
			w: 100; h: 20;
		}


		// directRam bus


		line {x1:-6; y1:-96; x2:-326; y2:-95;}
		line {x1:-327; y1:-186; x2:-326; y2:-95;}
		line {x1:-72; y1:-52; x2:-261; y2:-252;}
	}
}