schema_editor/examples/simplified FRISC model/comdel.system

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2022-05-25 05:39:45 +00:00
// Version 0.0.1
#include "libraries\frisc\vjezba1\FRISC.cdl"
#include "libraries\frisc\vjezba1\memory.cdl"
component System
{
clock 100MHz;
//directRam
wire INT;
//glavnaSabirnica
wire<32> ADR;
wire<32> DATA;
wire READ;
wire WRITE;
wired_and WAIT;
wired_and INT0;
wired_and INT1;
wired_and INT2;
wired_and INT3;
wire<3> SIZE;
wire --IACK;
wire --BREQ;
wire --BACK;
// components --------------------------------------------
subcomponent Memorija memorija<false, 1, 65536, 8, 0>(ADR, DATA, READ, WRITE, SIZE, WAIT, INT);
subcomponent FRISC procesor(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, INT1, INT2, INT3, --IACK, 1, *, INT) uses memorija;
display {
component { x: -12; y: 68; ref: "memorija"; }
component { x: -206; y: -76; ref: "procesor"; }
// directRam bus
// glavnaSabirnica bus
rectangle {
x: -222; y: 130;
w: 100; h: 20;
}
line {x1:-28; y1:96; x2:-90; y2:-26;}
line {x1:38; y1:52; x2:-171; y2:140;}
line {x1:-156; y1:40; x2:-171; y2:140;}
}
}