schema_editor/examples/simplified FRISC model/comdel.system

// Version 0.0.1
#include "libraries\frisc\vjezba1\FRISC.cdl"
#include "libraries\frisc\vjezba1\dma.cdl"
#include "libraries\frisc\vjezba1\memory.cdl"



component System
{
  clock 100MHz;
	//glavnaSabirnica
	wire<32> ADR;
	wire<32> DATA;
	wire READ;
	wire WRITE;
	wired_and WAIT;
	wired_and INT0;
	wired_and INT1;
	wired_and INT2;
	wired_and INT3;
	wire<3> SIZE;
	wire --IACK;
	wire --BREQ;
	wire --BACK;


	//PIOSabirnica
	wire<8> PIO_DATA;
	wire READY;
	wire STROBE;


	//directRam
	wire INT;


	// components --------------------------------------------
	subcomponent Memorija memorija<false, 1, 1024, 8, 0>(ADR, DATA, READ, WRITE, SIZE, WAIT, INT, *, *, *);
	subcomponent FRISC procesor(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, INT1, INT2, INT3, --IACK, 1, *, INT, *, *, *);
	subcomponent DMA dma<1024>(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, --BREQ, --BACK, 0, 0, *, *);

	display {
		component { x: -104; y: -102; ref: "procesor"; }
		component { x: 39; y: 199; ref: "memorija"; }
		component { x: -352; y: 13; ref: "dma"; }

		// glavnaSabirnica bus

		rectangle {
			x: -106; y: 80;
			w: 100; h: 20;
		}


		// PIOSabirnica bus


		// directRam bus


		line {x1:-54; y1:14; x2:-55; y2:90;}
		line {x1:89; y1:183; x2:-55; y2:90;}
		line {x1:-236; y1:51; x2:-55; y2:90;}
		line {x1:23; y1:227; x2:12; y2:-52;}
	}
}