Fixed schema generation

This commit is contained in:
Borna Rajković committed 2022-06-06 01:10:11 +02:00
1 parent 9b7ede933a
commit 1ec8b10ef5
7 files changed
+196 -20

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@@ -0,0 +1,66 @@
// Version 0.0.1
#include "libraries\frisc\vjezba1\FRISC.cdl"
#include "libraries\frisc\vjezba1\dma.cdl"
#include "libraries\frisc\vjezba1\memory.cdl"
component System
{
clock 100MHz;
//glavnaSabirnica
wire<32> ADR;
wire<32> DATA;
wire READ;
wire WRITE;
wired_and WAIT;
wired_and INT0;
wired_and INT1;
wired_and INT2;
wired_and INT3;
wire<3> SIZE;
wire --IACK;
wire --BREQ;
wire --BACK;
//PIOSabirnica
wire<8> PIO_DATA;
wire READY;
wire STROBE;
//directRam
wire INT;
// components --------------------------------------------
subcomponent Memorija memorija<false, 1, 1024, 8, 0>(ADR, DATA, READ, WRITE, SIZE, WAIT, INT, *, *, *);
subcomponent FRISC procesor(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, INT1, INT2, INT3, --IACK, 1, *, INT, *, *, *);
subcomponent DMA dma<1024>(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, --BREQ, --BACK, 0, 0, *, *);
display {
component { x: -104; y: -102; ref: "procesor"; }
component { x: 39; y: 199; ref: "memorija"; }
component { x: -352; y: 13; ref: "dma"; }
// glavnaSabirnica bus
rectangle {
x: -106; y: 80;
w: 100; h: 20;
}
// PIOSabirnica bus
// directRam bus
line {x1:-54; y1:14; x2:-55; y2:90;}
line {x1:89; y1:183; x2:-55; y2:90;}
line {x1:-244; y1:79; x2:-55; y2:90;}
line {x1:23; y1:227; x2:12; y2:-52;}
}
}
@@ -72,6 +72,7 @@
orientation: "right";
}
}
@wires{null, null, null, null}
}
}
@@ -214,6 +215,7 @@
orientation: "left";
}
}
@wires{null, null, null, null}
}
}
@@ -280,7 +282,7 @@
}
*/
pin {
x: 100; y: 50; w: 16; h: 16;
x: 100; y: 30; w: 16; h: 16;
}
}
}
@@ -290,7 +292,7 @@
@connection optional("COMDEL se ne može stvoriti. DMA nije spojen na nesto!")
@display {
pin {
x: 0; y: 0; w: 0; h: 0;
x: 100; y: 7; w: 16; h: 16;
}
}
@wires { 0, 0, null, null}
@@ -374,7 +376,7 @@
@wires{ADR, DATA, READ, WRITE, SIZE, WAIT, interupt, BREQ, BACK}
}
@connection (DMA.glavniPin, PIOSabirnica, FRISC.glavniPin) {
@connection (DMA.dodatnaPoveznica, PIOSabirnica, FRISC.glavniPin) {
@wires{PIO_DATA, READY, STROBE}
@wires{PIO_DATA, READY, STROBE}
}
@@ -0,0 +1,36 @@
@source "/home/bbr/Documents/Personal/FER/schema_editor/examples/simplified FRISC model/frisc_library.csl"
@schema {
@instance procesor FRISC {
@position (-162, -117)
@attribute _memory null
}
@instance dma DMA {
@position (-393, -26)
@attribute pocetnaAdresa 0
}
@instance glavnaSabirnica glavnaSabirnica {
@position (-155, 49)
@size 100
}
@instance PIOSabirnica PIOSabirnica {
@position (0, 0)
@size 0
}
@instance PIOSabirnica PIOSabirnica {
@position (0, 0)
@size 0
}
@connection (dma.glavniPin, PIOSabirnica, procesor.glavniPin) {
}
@connection (dma.glavniPin, glavnaSabirnica) {
@attribute interupt 1
}
@connection (dma.glavniPin, PIOSabirnica, procesor.glavniPin) {
}
}
@@ -0,0 +1,49 @@
@source "/home/bbr/Documents/Personal/FER/schema_editor/examples/simplified FRISC model/frisc_library.csl"
@schema {
@instance procesor FRISC {
@position (-104, -102)
@attribute _memory null
}
@instance memorija Memorija {
@position (39, 199)
@attribute sinkroniziran false
@attribute brzina 1
@attribute kapacitet 1024
@attribute size 8
@attribute pocetnaAdresa 0
}
@instance dma DMA {
@position (-352, 13)
@attribute pocetnaAdresa 1024
}
@instance glavnaSabirnica glavnaSabirnica {
@position (-106, 80)
@size 100
}
@instance PIOSabirnica PIOSabirnica {
@position (0, 0)
@size -1
}
@instance directRam directRam {
@position (0, 0)
@size -1
}
@connection (procesor.glavniPin, glavnaSabirnica) {
}
@connection (memorija.glavniPin, glavnaSabirnica) {
}
@connection (dma.glavniPin, glavnaSabirnica) {
@attribute interupt INT0
}
@connection (memorija.memDirect, directRam, procesor.memDirect) {
@attribute procConn "INT"
@attribute memConn "INT"
}
}