Extracted schema and library management to Application
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@@ -7,7 +7,7 @@
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component System
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{
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clock 100MHz;
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//glavnaSabirnica
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//bus
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wire<32> ADR;
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wire<32> DATA;
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wire READ;
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@@ -28,17 +28,21 @@ component System
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// components --------------------------------------------
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subcomponent Memorija memorija<false, 1, 65536, 8, 0>(ADR, DATA, READ, WRITE, SIZE, WAIT, INT);
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subcomponent FRISC procesor(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, INT1, INT2, INT3, --IACK, 1, *, INT) uses memorija;
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subcomponent Memorija mem<false, 1, 1024, 8, 1024>(ADR, DATA, READ, WRITE, SIZE, WAIT, INT);
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subcomponent FRISC proc(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, INT1, INT2, INT3, --IACK, 1, *, INT);
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subcomponent FRISC procesor(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, INT1, INT2, INT3, --IACK, 1, *, 93852075053817, 0, null, null);
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subcomponent FRISC procesor(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, INT1, INT2, INT3, --IACK, 1, *, 93852075053817, 0, null, null);
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display {
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component { x: -582; y: -296; ref: "procesor"; }
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component { x: -446; y: -12; ref: "memorija"; }
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component { x: 0; y: 0; ref: "proc"; }
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component { x: 0; y: 250; ref: "mem"; }
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component { x: -185; y: 9; ref: "procesor"; }
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component { x: -181; y: 194; ref: "procesor"; }
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// glavnaSabirnica bus
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// bus bus
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rectangle {
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x: -581; y: -37;
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x: 0; y: 200;
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w: 100; h: 20;
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}
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@@ -46,8 +50,10 @@ component System
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// directRam bus
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line {x1:-532; y1:-180; x2:-530; y2:-26;}
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line {x1:-462; y1:16; x2:-466; y2:-246;}
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line {x1:-396; y1:-28; x2:-530; y2:-26;}
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line {x1:50; y1:116; x2:50; y2:210;}
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line {x1:50; y1:234; x2:50; y2:210;}
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line {x1:-16; y1:278; x2:116; y2:50;}
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line {x1:-135; y1:125; x2:50; y2:210;}
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line {x1:-131; y1:310; x2:50; y2:210;}
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}
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}
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