Extracted schema and library management to Application

This commit is contained in:
Borna Rajković committed 2022-05-30 23:11:06 +02:00
1 parent 0c4afe87d9
commit 86b8861533
12 files changed
+334 -182

No files matched your search

+16 -10
View File
@@ -7,7 +7,7 @@
component System
{
clock 100MHz;
//glavnaSabirnica
//bus
wire<32> ADR;
wire<32> DATA;
wire READ;
@@ -28,17 +28,21 @@ component System
// components --------------------------------------------
subcomponent Memorija memorija<false, 1, 65536, 8, 0>(ADR, DATA, READ, WRITE, SIZE, WAIT, INT);
subcomponent FRISC procesor(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, INT1, INT2, INT3, --IACK, 1, *, INT) uses memorija;
subcomponent Memorija mem<false, 1, 1024, 8, 1024>(ADR, DATA, READ, WRITE, SIZE, WAIT, INT);
subcomponent FRISC proc(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, INT1, INT2, INT3, --IACK, 1, *, INT);
subcomponent FRISC procesor(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, INT1, INT2, INT3, --IACK, 1, *, 93852075053817, 0, null, null);
subcomponent FRISC procesor(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, INT1, INT2, INT3, --IACK, 1, *, 93852075053817, 0, null, null);
display {
component { x: -582; y: -296; ref: "procesor"; }
component { x: -446; y: -12; ref: "memorija"; }
component { x: 0; y: 0; ref: "proc"; }
component { x: 0; y: 250; ref: "mem"; }
component { x: -185; y: 9; ref: "procesor"; }
component { x: -181; y: 194; ref: "procesor"; }
// glavnaSabirnica bus
// bus bus
rectangle {
x: -581; y: -37;
x: 0; y: 200;
w: 100; h: 20;
}
@@ -46,8 +50,10 @@ component System
// directRam bus
line {x1:-532; y1:-180; x2:-530; y2:-26;}
line {x1:-462; y1:16; x2:-466; y2:-246;}
line {x1:-396; y1:-28; x2:-530; y2:-26;}
line {x1:50; y1:116; x2:50; y2:210;}
line {x1:50; y1:234; x2:50; y2:210;}
line {x1:-16; y1:278; x2:116; y2:50;}
line {x1:-135; y1:125; x2:50; y2:210;}
line {x1:-131; y1:310; x2:50; y2:210;}
}
}