// Version 0.0.1
#include "libraries\frisc\vjezba1\FRISC.cdl"
#include "libraries\frisc\vjezba1\memory.cdl"



component System
{
  clock 100MHz;
	//bus
	wire<32> ADR;
	wire<32> DATA;
	wire READ;
	wire WRITE;
	wired_and WAIT;
	wired_and INT0;
	wired_and INT1;
	wired_and INT2;
	wired_and INT3;
	wire<3> SIZE;
	wire --IACK;
	wire --BREQ;
	wire --BACK;


	// components --------------------------------------------
	subcomponent Memorija mem<false, 1, 1024, 8, 1024>(ADR, DATA, READ, WRITE, SIZE, WAIT, 94534054858378, 0, null, null);
	subcomponent FRISC procesor_002(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, INT1, INT2, INT3, --IACK, 1, *, 94534054858378, 0, null, null);
	subcomponent FRISC procesor_001(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, INT1, INT2, INT3, --IACK, 1, *, 94534054858378, 0, null, null);
	subcomponent FRISC procesor_000(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, INT1, INT2, INT3, --IACK, 1, *, 94534054858378, 0, null, null);
	subcomponent FRISC procesor(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, INT1, INT2, INT3, --IACK, 1, *, 94534054858378, 0, null, null);

	display {
		component { x: 0; y: 0; ref: "procesor_002"; }
		component { x: 0; y: 250; ref: "mem"; }
		component { x: -89; y: 74; ref: "procesor_001"; }
		component { x: -175; y: 195; ref: "procesor_000"; }
		component { x: -195; y: 63; ref: "procesor"; }

		// bus bus

		rectangle {
			x: 0; y: 200;
			w: 100; h: 20;
		}


		line {x1:50; y1:116; x2:50; y2:210;}
		line {x1:50; y1:234; x2:50; y2:210;}
		line {x1:-39; y1:190; x2:50; y2:210;}
		line {x1:-145; y1:179; x2:50; y2:210;}
		line {x1:-125; y1:311; x2:50; y2:210;}
	}
}