// Version 0.0.1
#include "libraries\frisc\vjezba1\FRISC.cdl"
#include "libraries\frisc\vjezba1\memory.cdl"



component System
{
  clock 100MHz;
	//bus
	wire<32> ADR;
	wire<32> DATA;
	wire READ;
	wire WRITE;
	wired_and WAIT;
	wired_and INT0;
	wired_and INT1;
	wired_and INT2;
	wired_and INT3;
	wire<3> SIZE;
	wire --IACK;
	wire --BREQ;
	wire --BACK;


	//directRam
	wire INT;


	// components --------------------------------------------
	subcomponent Memorija mem<false, 1, 1024, 8, 1024>(ADR, DATA, READ, WRITE, SIZE, WAIT, INT);
	subcomponent FRISC proc(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, INT1, INT2, INT3, --IACK, 1, *, INT);
	subcomponent FRISC procesor(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, INT1, INT2, INT3, --IACK, 1, *, 93852075053817, 0, null, null);
	subcomponent FRISC procesor(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, INT1, INT2, INT3, --IACK, 1, *, 93852075053817, 0, null, null);

	display {
		component { x: 0; y: 0; ref: "proc"; }
		component { x: 0; y: 250; ref: "mem"; }
		component { x: -185; y: 9; ref: "procesor"; }
		component { x: -181; y: 194; ref: "procesor"; }

		// bus bus

		rectangle {
			x: 0; y: 200;
			w: 100; h: 20;
		}


		// directRam bus


		line {x1:50; y1:116; x2:50; y2:210;}
		line {x1:50; y1:234; x2:50; y2:210;}
		line {x1:-16; y1:278; x2:116; y2:50;}
		line {x1:-135; y1:125; x2:50; y2:210;}
		line {x1:-131; y1:310; x2:50; y2:210;}
	}
}