53 lines
1.0 KiB
Plaintext
53 lines
1.0 KiB
Plaintext
// Version 0.0.1
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#include "libraries\frisc\vjezba1\FRISC.cdl"
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#include "libraries\frisc\vjezba1\memory.cdl"
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component System
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{
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clock 100MHz;
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//glavnaSabirnica
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wire<32> ADR;
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wire<32> DATA;
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wire READ;
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wire WRITE;
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wired_and WAIT;
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wired_and INT0;
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wired_and INT1;
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wired_and INT2;
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wired_and INT3;
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wire<3> SIZE;
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wire --IACK;
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wire --BREQ;
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wire --BACK;
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//directRam
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wire INT;
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// components --------------------------------------------
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subcomponent Memorija memorija<false, 1, 65536, 8, 0>(ADR, DATA, READ, WRITE, SIZE, WAIT, INT);
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subcomponent FRISC procesor(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, INT1, INT2, INT3, --IACK, 1, *, INT) uses memorija;
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display {
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component { x: -582; y: -296; ref: "procesor"; }
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component { x: -446; y: -12; ref: "memorija"; }
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// glavnaSabirnica bus
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rectangle {
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x: -581; y: -37;
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w: 100; h: 20;
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}
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// directRam bus
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line {x1:-532; y1:-180; x2:-530; y2:-26;}
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line {x1:-462; y1:16; x2:-466; y2:-246;}
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line {x1:-396; y1:-28; x2:-530; y2:-26;}
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}
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} |