66 lines
1.3 KiB
Plaintext
66 lines
1.3 KiB
Plaintext
// Version 0.0.1
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#include "libraries\frisc\vjezba1\FRISC.cdl"
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#include "libraries\frisc\vjezba1\dma.cdl"
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#include "libraries\frisc\vjezba1\memory.cdl"
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component System
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{
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clock 100MHz;
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//glavnaSabirnica
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wire<32> ADR;
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wire<32> DATA;
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wire READ;
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wire WRITE;
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wired_and WAIT;
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wired_and INT0;
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wired_and INT1;
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wired_and INT2;
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wired_and INT3;
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wire<3> SIZE;
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wire --IACK;
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wire --BREQ;
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wire --BACK;
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//PIOSabirnica
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wire<8> PIO_DATA;
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wire READY;
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wire STROBE;
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//directRam
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wire INT;
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// components --------------------------------------------
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subcomponent Memorija memorija<false, 1, 1024, 8, 0>(ADR, DATA, READ, WRITE, SIZE, WAIT, INT, *, *, *);
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subcomponent FRISC procesor(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, INT1, INT2, INT3, --IACK, 1, *, INT, *, *, *);
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subcomponent DMA dma<1024>(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, --BREQ, --BACK, 0, 0, *, *);
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display {
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component { x: -104; y: -102; ref: "procesor"; }
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component { x: 39; y: 199; ref: "memorija"; }
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component { x: -352; y: 13; ref: "dma"; }
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// glavnaSabirnica bus
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rectangle {
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x: -106; y: 80;
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w: 100; h: 20;
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}
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// PIOSabirnica bus
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// directRam bus
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line {x1:-54; y1:14; x2:-55; y2:90;}
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line {x1:89; y1:183; x2:-55; y2:90;}
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line {x1:-236; y1:51; x2:-55; y2:90;}
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line {x1:23; y1:227; x2:12; y2:-52;}
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}
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} |