54 lines
1.6 KiB
Plaintext
54 lines
1.6 KiB
Plaintext
// Version 0.0.1
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#include "libraries\frisc\vjezba1\FRISC.cdl"
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#include "libraries\frisc\vjezba1\memory.cdl"
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component System
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{
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clock 100MHz;
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//bus
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wire<32> ADR;
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wire<32> DATA;
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wire READ;
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wire WRITE;
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wired_and WAIT;
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wired_and INT0;
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wired_and INT1;
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wired_and INT2;
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wired_and INT3;
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wire<3> SIZE;
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wire --IACK;
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wire --BREQ;
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wire --BACK;
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// components --------------------------------------------
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subcomponent Memorija mem<false, 1, 1024, 8, 1024>(ADR, DATA, READ, WRITE, SIZE, WAIT, 94534054858378, 0, null, null);
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subcomponent FRISC procesor_002(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, INT1, INT2, INT3, --IACK, 1, *, 94534054858378, 0, null, null);
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subcomponent FRISC procesor_001(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, INT1, INT2, INT3, --IACK, 1, *, 94534054858378, 0, null, null);
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subcomponent FRISC procesor_000(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, INT1, INT2, INT3, --IACK, 1, *, 94534054858378, 0, null, null);
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subcomponent FRISC procesor(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, INT1, INT2, INT3, --IACK, 1, *, 94534054858378, 0, null, null);
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display {
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component { x: 0; y: 0; ref: "procesor_002"; }
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component { x: 0; y: 250; ref: "mem"; }
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component { x: -89; y: 74; ref: "procesor_001"; }
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component { x: -175; y: 195; ref: "procesor_000"; }
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component { x: -195; y: 63; ref: "procesor"; }
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// bus bus
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rectangle {
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x: 0; y: 200;
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w: 100; h: 20;
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}
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line {x1:50; y1:116; x2:50; y2:210;}
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line {x1:50; y1:234; x2:50; y2:210;}
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line {x1:-39; y1:190; x2:50; y2:210;}
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line {x1:-145; y1:179; x2:50; y2:210;}
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line {x1:-125; y1:311; x2:50; y2:210;}
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}
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} |