Basic refactor

examples/simplified FRISC model/comdel.system

@@ -7,10 +7,6 @@
 component System
 {
   clock 100MHz;
-	//directRam
-	wire INT;
-
-
 	//glavnaSabirnica
 	wire<32> ADR;
 	wire<32> DATA;
@@ -27,27 +23,31 @@ component System
 	wire --BACK;
 
 
+	//directRam
+	wire INT;
+
+
 	// components --------------------------------------------
 	subcomponent Memorija memorija<false, 1, 65536, 8, 0>(ADR, DATA, READ, WRITE, SIZE, WAIT, INT);
 	subcomponent FRISC procesor(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, INT1, INT2, INT3, --IACK, 1, *, INT) uses memorija;
 
 	display {
-		component { x: -12; y: 68; ref: "memorija"; }
-		component { x: -206; y: -76; ref: "procesor"; }
-
-		// directRam bus
-
+		component { x: -582; y: -296; ref: "procesor"; }
+		component { x: -446; y: -12; ref: "memorija"; }
 
 		// glavnaSabirnica bus
 
 		rectangle {
-			x: -222; y: 130;
+			x: -581; y: -37;
 			w: 100; h: 20;
 		}
 
 
-		line {x1:-28; y1:96; x2:-90; y2:-26;}
-		line {x1:38; y1:52; x2:-171; y2:140;}
-		line {x1:-156; y1:40; x2:-171; y2:140;}
+		// directRam bus
+
+
+		line {x1:-532; y1:-180; x2:-530; y2:-26;}
+		line {x1:-462; y1:16; x2:-466; y2:-246;}
+		line {x1:-396; y1:-28; x2:-530; y2:-26;}
 	}
 }

examples/simplified FRISC model/schema3.csl

@@ -1,8 +1,13 @@
 @source "/home/bbr/Documents/Personal/FER/schema_editor/examples/simplified FRISC model/frisc_library.csl"
 
 @schema {
+	@instance procesor FRISC {
+		@position (-76, -97)
+		@attribute _memory memorija
+	}
+
 	@instance memorija Memorija {
-		@position (-12, 68)
+		@position (52, 119)
 		@attribute sinkroniziran false
 		@attribute brzina 1
 		@attribute kapacitet 65536
@@ -10,9 +15,9 @@
 		@attribute pocetnaAdresa 0
 	}
 
-	@instance procesor FRISC {
-		@position (-206, -76)
-		@attribute _memory memorija
+	@instance glavnaSabirnica glavnaSabirnica {
+		@position (-78, 88)
+		@size 100
 	}
 
 	@instance directRam directRam {
@@ -20,15 +25,10 @@
 		@size 0
 	}
 
-	@instance glavnaSabirnica glavnaSabirnica {
-		@position (-222, 130)
-		@size 50
-	}
-
-	@connection (memorija.memDirect, directRam, procesor.memDirect) {
-	}
 	@connection (memorija.glavniPin, glavnaSabirnica) {
 	}
 	@connection (procesor.glavniPin, glavnaSabirnica) {
 	}
+	@connection (memorija.memDirect, directRam, procesor.memDirect) {
+	}
 }