Refactored validation

This commit is contained in:
Borna Rajković committed 2022-06-14 00:53:46 +02:00
1 parent fe4a39803c
commit 7be3a1b5bc
29 files changed
+696 -545

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+20 -7
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@@ -1,5 +1,6 @@
// Version 0.0.1
#include "libraries\frisc\vjezba1\FRISC.cdl"
#include "libraries\frisc\vjezba1\dma.cdl"
#include "libraries\frisc\vjezba1\memory.cdl"
@@ -23,31 +24,43 @@ component System
wire --BACK;
//PIOSabirnica
wire<8> PIO_DATA;
wire READY;
wire STROBE;
//directRam
wire INT;
// components --------------------------------------------
subcomponent Memorija memorija<false, 1, 65536, 8, 0>(ADR, DATA, READ, WRITE, SIZE, WAIT, *, *, *, INT);
subcomponent Memorija memorija<false, 1, 1024, 8, 0>(ADR, DATA, READ, WRITE, SIZE, WAIT, INT, *, *, *);
subcomponent FRISC procesor(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, INT1, INT2, INT3, --IACK, 1, *, INT, *, *, *);
subcomponent DMA dma<1024>(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, --BREQ, --BACK, 0, 0, *, *);
display {
component { x: -377; y: -302; ref: "procesor"; }
component { x: -56; y: -80; ref: "memorija"; }
component { x: -104; y: -102; ref: "procesor"; }
component { x: 39; y: 199; ref: "memorija"; }
component { x: -352; y: 13; ref: "dma"; }
// glavnaSabirnica bus
rectangle {
x: -377; y: -106;
x: -106; y: 80;
w: 100; h: 20;
}
// PIOSabirnica bus
// directRam bus
line {x1:-6; y1:-96; x2:-326; y2:-95;}
line {x1:-327; y1:-186; x2:-326; y2:-95;}
line {x1:-72; y1:-52; x2:-261; y2:-252;}
line {x1:-54; y1:14; x2:-55; y2:90;}
line {x1:89; y1:183; x2:-55; y2:90;}
line {x1:-236; y1:51; x2:-55; y2:90;}
line {x1:23; y1:227; x2:12; y2:-52;}
}
}
+35 -2
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@@ -2,15 +2,48 @@
@schema {
@instance procesor FRISC {
@position (-543, -304)
@position (-104, -102)
@attribute _memory null
}
@instance memorija Memorija {
@position (39, 199)
@attribute sinkroniziran false
@attribute brzina 1
@attribute kapacitet 1024
@attribute size 8
@attribute pocetnaAdresa 0
}
@instance dma DMA {
@position (-352, 13)
@attribute pocetnaAdresa 1024
}
@instance glavnaSabirnica glavnaSabirnica {
@position (-544, -91)
@position (-106, 80)
@size 100
}
@instance PIOSabirnica PIOSabirnica {
@position (0, 0)
@size -1
}
@instance directRam directRam {
@position (0, 0)
@size -1
}
@connection (procesor.glavniPin, glavnaSabirnica) {
}
@connection (memorija.glavniPin, glavnaSabirnica) {
}
@connection (dma.glavniPin, glavnaSabirnica) {
@attribute interupt INT0
}
@connection (memorija.memDirect, directRam, procesor.memDirect) {
@attribute procConn "INT"
@attribute memConn "INT"
}
}