Refactored validation
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@@ -1,5 +1,6 @@
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// Version 0.0.1
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#include "libraries\frisc\vjezba1\FRISC.cdl"
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#include "libraries\frisc\vjezba1\dma.cdl"
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#include "libraries\frisc\vjezba1\memory.cdl"
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@@ -23,31 +24,43 @@ component System
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wire --BACK;
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//PIOSabirnica
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wire<8> PIO_DATA;
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wire READY;
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wire STROBE;
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//directRam
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wire INT;
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// components --------------------------------------------
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subcomponent Memorija memorija<false, 1, 65536, 8, 0>(ADR, DATA, READ, WRITE, SIZE, WAIT, *, *, *, INT);
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subcomponent Memorija memorija<false, 1, 1024, 8, 0>(ADR, DATA, READ, WRITE, SIZE, WAIT, INT, *, *, *);
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subcomponent FRISC procesor(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, INT1, INT2, INT3, --IACK, 1, *, INT, *, *, *);
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subcomponent DMA dma<1024>(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, --BREQ, --BACK, 0, 0, *, *);
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display {
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component { x: -377; y: -302; ref: "procesor"; }
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component { x: -56; y: -80; ref: "memorija"; }
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component { x: -104; y: -102; ref: "procesor"; }
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component { x: 39; y: 199; ref: "memorija"; }
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component { x: -352; y: 13; ref: "dma"; }
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// glavnaSabirnica bus
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rectangle {
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x: -377; y: -106;
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x: -106; y: 80;
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w: 100; h: 20;
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}
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// PIOSabirnica bus
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// directRam bus
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line {x1:-6; y1:-96; x2:-326; y2:-95;}
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line {x1:-327; y1:-186; x2:-326; y2:-95;}
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line {x1:-72; y1:-52; x2:-261; y2:-252;}
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line {x1:-54; y1:14; x2:-55; y2:90;}
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line {x1:89; y1:183; x2:-55; y2:90;}
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line {x1:-236; y1:51; x2:-55; y2:90;}
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line {x1:23; y1:227; x2:12; y2:-52;}
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}
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}
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@@ -2,15 +2,48 @@
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@schema {
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@instance procesor FRISC {
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@position (-543, -304)
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@position (-104, -102)
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@attribute _memory null
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}
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@instance memorija Memorija {
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@position (39, 199)
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@attribute sinkroniziran false
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@attribute brzina 1
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@attribute kapacitet 1024
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@attribute size 8
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@attribute pocetnaAdresa 0
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}
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@instance dma DMA {
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@position (-352, 13)
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@attribute pocetnaAdresa 1024
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}
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@instance glavnaSabirnica glavnaSabirnica {
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@position (-544, -91)
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@position (-106, 80)
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@size 100
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}
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@instance PIOSabirnica PIOSabirnica {
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@position (0, 0)
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@size -1
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}
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@instance directRam directRam {
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@position (0, 0)
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@size -1
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}
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@connection (procesor.glavniPin, glavnaSabirnica) {
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}
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@connection (memorija.glavniPin, glavnaSabirnica) {
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}
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@connection (dma.glavniPin, glavnaSabirnica) {
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@attribute interupt INT0
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}
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@connection (memorija.memDirect, directRam, procesor.memDirect) {
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@attribute procConn "INT"
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@attribute memConn "INT"
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}
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}
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