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Updated component and bus generation logic + bugfixes

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Borna Rajković committed 2022-05-31 01:05:08 +02:00
1 parent 86b8861533
commit f93a2afa63
14 files changed
+208 -68
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examples/simplified FRISC model/comdel.system
+12 -17
View File
@@ -23,21 +23,19 @@ component System
wire --BACK;
//directRam
wire INT;
// components --------------------------------------------
subcomponent Memorija mem<false, 1, 1024, 8, 1024>(ADR, DATA, READ, WRITE, SIZE, WAIT, INT);
subcomponent FRISC proc(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, INT1, INT2, INT3, --IACK, 1, *, INT);
subcomponent FRISC procesor(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, INT1, INT2, INT3, --IACK, 1, *, 93852075053817, 0, null, null);
subcomponent FRISC procesor(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, INT1, INT2, INT3, --IACK, 1, *, 93852075053817, 0, null, null);
subcomponent Memorija mem<false, 1, 1024, 8, 1024>(ADR, DATA, READ, WRITE, SIZE, WAIT, 94534054858378, 0, null, null);
subcomponent FRISC procesor_002(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, INT1, INT2, INT3, --IACK, 1, *, 94534054858378, 0, null, null);
subcomponent FRISC procesor_001(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, INT1, INT2, INT3, --IACK, 1, *, 94534054858378, 0, null, null);
subcomponent FRISC procesor_000(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, INT1, INT2, INT3, --IACK, 1, *, 94534054858378, 0, null, null);
subcomponent FRISC procesor(ADR, DATA, READ, WRITE, SIZE, WAIT, INT0, INT1, INT2, INT3, --IACK, 1, *, 94534054858378, 0, null, null);
display {
component { x: 0; y: 0; ref: "proc"; }
component { x: 0; y: 0; ref: "procesor_002"; }
component { x: 0; y: 250; ref: "mem"; }
component { x: -185; y: 9; ref: "procesor"; }
component { x: -181; y: 194; ref: "procesor"; }
component { x: -89; y: 74; ref: "procesor_001"; }
component { x: -175; y: 195; ref: "procesor_000"; }
component { x: -195; y: 63; ref: "procesor"; }
// bus bus
@@ -47,13 +45,10 @@ component System
}
// directRam bus
line {x1:50; y1:116; x2:50; y2:210;}
line {x1:50; y1:234; x2:50; y2:210;}
line {x1:-16; y1:278; x2:116; y2:50;}
line {x1:-135; y1:125; x2:50; y2:210;}
line {x1:-131; y1:310; x2:50; y2:210;}
line {x1:-39; y1:190; x2:50; y2:210;}
line {x1:-145; y1:179; x2:50; y2:210;}
line {x1:-125; y1:311; x2:50; y2:210;}
}
}
examples/simplified FRISC model/frisc_library.csl
+6 -3
View File
@@ -18,7 +18,7 @@
}
@component FRISC processor {
@instanceName "procesor"
@instanceName procesor
@tooltip "Procesor FRISC, mora postojati jedan"
@count (1, 1)
@source "FRISC.cdl"
@@ -77,7 +77,7 @@
}
@component Memorija memory {
@instanceName "memorija"
@instanceName memorija
@tooltip "Memorijska komponenta, mora postojati barem jedna"
@count (1,1000)
@source "memory.cdl"
@@ -219,7 +219,7 @@
}
@component DMA {
@instanceName "dma"
@instanceName dma
@tooltip "DMA-kontroler"
@count (0,1000)
@source "dma.cdl"
@@ -299,6 +299,7 @@
}
@bus glavnaSabirnica regular {
@instanceName glavnaSabirnica
@tooltip "sabirnica za spajanje FRISC a s memorijama i UI/jedinicama"
@count (1,1)
@display {
@@ -334,6 +335,7 @@
}
}
@bus PIOSabirnica automatic {
@instanceName PIOSabirnica
@count (0, 20)
@wires {
PIO_DATA<8>,
@@ -343,6 +345,7 @@
}
@bus directRam automatic {
@instanceName directRam
@wires {
INT
}
examples/simplified FRISC model/schema2.csl
+18 -1
View File
@@ -1,7 +1,7 @@
@source "frisc_library.csl"
@schema {
@instance proc FRISC {
@instance procesor_002 FRISC {
@position (0, 0)
@attribute _memory null
}
@@ -15,11 +15,28 @@
@attribute pocetnaAdresa 1024
}
@instance procesor_001 FRISC {
@position (-89, 74)
@attribute _memory null
}
@instance procesor_000 FRISC {
@position (-175, 195)
@attribute _memory null
}
@instance procesor FRISC {
@position (-195, 63)
@attribute _memory null
}
@instance bus glavnaSabirnica {
@position (0, 200)
@size 100
}
@connection (procesor_002.glavniPin, bus) {
}
@connection (mem.glavniPin, bus) {
}
}