Borna Rajković f93a2afa63 Updated component and bus generation logic + bugfixes		2022-05-31 01:05:08 +02:00
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comdel.system	Updated component and bus generation logic + bugfixes	2022-05-31 01:05:08 +02:00
frisc_library.csl	Updated component and bus generation logic + bugfixes	2022-05-31 01:05:08 +02:00
schema.csl	Added count and pin validators	2022-05-20 00:44:40 +02:00
schema2.csl	Updated component and bus generation logic + bugfixes	2022-05-31 01:05:08 +02:00
schema3.csl	Basic refactor	2022-05-27 08:18:17 +02:00